Technology: Chip architects turn to trench warfare

 作者:暨泓     |      日期:2019-03-04 03:11:09
By LEON CLIFFORD EACH DRAM cell can store one bit of binary information. The cell consists of a transistor and a capacitor. It is set either as a one or a zero, depending on whether or not the capacitor is charged. The transistor, which is basically a switch, controls the charge on the capacitor and can switch the cell from state to state by charging or discharging the capacitor. It is more difficult to shrink capacitors than transistors, because capacitors need a certain amount of volume in order to store charge. The smaller the capacitor, the less charge it can store. It is difficult to maintain very small charges because they tend to leak away, and it is difficult to detect and turn them on and off because they tend to be drowned in electrical noise. So chip makers have had to find a way of cramming more detail onto the surface of each DRAM without reducing the volume of the capacitors. One way is to use the third dimension. Traditional, flat capacitors take up too much surface area. However, engineers can reduce the surface area dramatically by turning the capacitors on their side and burying them in trenches. Many of the 4-megabit DRAMs currently use ‘trenched’ capacitors. But there is a limit to the number of trenches that will fit onto a chip. Manufacturers have, therefore, developed a technique called ‘stacking’ to meet the inevitable demand for even greater chip densities. Stacking, like trenching, uses the third dimension. But instead of putting one capacitor into a trench, the idea is to build a stack of several capacitors on top of each other, using an area no greater than that of a conventional flat capacitor. As DRAM densities increase,